添加启动文件
- 正常不需要添加启动文件，生成的时候已经添加好了，由于个别电脑的问题，需要手动添加
- 打开生成的MDK工程.uvprojx
- Manage Project Items添加Groups->
MDK-ARM
- 在
MDK-ARM组里添加MDK-ARM文件价里的文件startup_stm32f103xe.s
工程详解
main.c文件
HAL_Init()函数
HAL_Init()函数，重置所有外围设备，初始化闪存接口和Systick,里边会回调stm32f1xx_hal_msp.c的HAL_MspInit函数HAL_MspInit函数配置了调试端口的重映射，对应我们选择的SW-DP模式
SystemClock_Config()函数
- 系统时钟配置函数，和SPl库不同的是，HAL库没有初始化时钟,需要自己配置
- 此函数对应我们在时钟配置里的选择
RCC内/外部振荡器配置结构体分析
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
| /**
* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
*/
typedef struct
{
uint32_t OscillatorType; /*!< The oscillators to be configured.
This parameter can be a value of @ref RCC_Oscillator_Type */
#if defined(STM32F105xC) || defined(STM32F107xC)
uint32_t Prediv1Source; /*!< The Prediv1 source value.
This parameter can be a value of @ref RCCEx_Prediv1_Source */
#endif /* STM32F105xC || STM32F107xC */
uint32_t HSEState; /*!< The new state of the HSE.
This parameter can be a value of @ref RCC_HSE_Config */
uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM)
This parameter can be a value of @ref RCCEx_Prediv1_Factor */
uint32_t LSEState; /*!< The new state of the LSE.
This parameter can be a value of @ref RCC_LSE_Config */
uint32_t HSIState; /*!< The new state of the HSI.
This parameter can be a value of @ref RCC_HSI_Config */
uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
uint32_t LSIState; /*!< The new state of the LSI.
This parameter can be a value of @ref RCC_LSI_Config */
RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
#if defined(STM32F105xC) || defined(STM32F107xC)
RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */
#endif /* STM32F105xC || STM32F107xC */
} RCC_OscInitTypeDef;
|
1
2
3
4
5
6
7
8
| /** @defgroup RCC_Oscillator_Type Oscillator Type
* @{
*/
#define RCC_OSCILLATORTYPE_NONE 0x00000000U //此次配置不配置振荡器
#define RCC_OSCILLATORTYPE_HSE 0x00000001U //外部高速振荡器
#define RCC_OSCILLATORTYPE_HSI 0x00000002U //内部高速振荡器
#define RCC_OSCILLATORTYPE_LSE 0x00000004U //外部低速振荡器
#define RCC_OSCILLATORTYPE_LSI 0x00000008U //内部低速振荡器
|
1
2
3
4
5
6
7
8
9
10
11
12
| #if defined(STM32F105xC) || defined(STM32F107xC)
/** @defgroup RCCEx_Prediv1_Source Prediv1 Source
* @{
*/
#define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE //HSE
#define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2 //PLL2
/**
* @}
*/
#endif /* STM32F105xC || STM32F107xC */
|
注：仅在STM32F105xC和STM32F107xC系列单片机使用
1
2
3
4
5
6
| /** @defgroup RCC_HSE_Config HSE Config
* @{
*/
#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation *///失效
#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation *///外部振荡器，如无源晶振
#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock *///外部时钟源，如有源晶振
|
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
| /** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor
* @{
*/
#define RCC_HSE_PREDIV_DIV1 0x00000000U //不分频
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
|| defined(STM32F100xE)
#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2 //分频2
#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3 //分频3
#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4 //分频4
#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5 //分频5
#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6 //分频6
#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7 //分频7
#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8 //分频8
#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9 //分频9
#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10 //分频10
#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11 //分频11
#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12 //分频12
#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13 //分频13
#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14 //分频14
#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15 //分频15
#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16 //分频16
#else
#define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE //分频2
#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
|
1
2
3
4
5
6
| /** @defgroup RCC_LSE_Config LSE Config
* @{
*/
#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation *///失效
#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation *///外部振荡器，如无源晶振
#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock *///外部时钟源，如有源晶振
|
1
2
3
4
5
| /** @defgroup RCC_HSI_Config HSI Config
* @{
*/
#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation *///失效
#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation *///开启
|
- HSI校准微调值
HSICalibrationValue
1
| #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value *///默认校准值
|
注：范围是0x00-0x1F
1
2
3
4
5
| /** @defgroup RCC_LSI_Config LSI Config
* @{
*/
#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation *///失效
#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation *///开启
|
- PLL结构体参数
PLL
- PLL2结构体参数
PLL2
PLL结构体分析
1
2
3
4
5
6
7
8
9
10
11
12
13
14
| /**
* @brief RCC PLL configuration structure definition
*/
typedef struct
{
uint32_t PLLState; /*!< PLLState: The new state of the PLL.
This parameter can be a value of @ref RCC_PLL_Config */
uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
This parameter must be a value of @ref RCC_PLL_Clock_Source */
uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
} RCC_PLLInitTypeDef
|
1
2
3
4
5
6
| /** @defgroup RCC_PLL_Config PLL Config
* @{
*/
#define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured *///不配置PLL
#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation *///PLL关闭
#define RCC_PLL_ON 0x00000002U /*!< PLL activation *///PLL开启
|
1
2
3
4
5
6
| /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
* @{
*/
#define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source *///内部高速振荡器2分频
#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source *///外部高速振荡器
|
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
| /** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor
* @{
*/
#if defined(STM32F105xC) || defined(STM32F107xC)
#else
#define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2 //2倍频
#define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3 //3倍频
#endif /* STM32F105xC || STM32F107xC */
#define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4 //4倍频
#define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5 //5倍频
#define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6 //6倍频
#define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7 //7倍频
#define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8 //8倍频
#define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9 //9倍频
#if defined(STM32F105xC) || defined(STM32F107xC)
#define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5 //6.5倍频
#else
#define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10 //10倍频
#define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11 //11倍频
#define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12 //12倍频
#define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13 //13倍频
#define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14 //14倍频
#define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15 //15倍频
#define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16 //16倍频
#endif /* STM32F105xC || STM32F107xC */
|
PLL2结构体分析
- 注：仅在
STM32F105xC和STM32F107xC系列单片机使用
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
| #if defined(STM32F105xC) || defined(STM32F107xC)
/**
* @brief RCC PLL2 configuration structure definition
*/
typedef struct
{
uint32_t PLL2State; /*!< The new state of the PLL2.This parameter can be a value of @ref RCCEx_PLL2_Config */
uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock.This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/
#if defined(STM32F105xC) || defined(STM32F107xC)
uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.This parameter can be a value of @ref RCCEx_Prediv2_Factor */
#endif /* STM32F105xC || STM32F107xC */
} RCC_PLL2InitTypeDef;
#endif /* STM32F105xC || STM32F107xC */
|
1
2
3
4
5
6
| /** @defgroup RCCEx_PLL2_Config PLL Config
* @{
*/
#define RCC_PLL2_NONE 0x00000000U //不配置
#define RCC_PLL2_OFF 0x00000001U //关闭
#define RCC_PLL2_ON 0x00000002U //开启
|
1
2
3
4
5
6
7
8
9
10
11
12
13
| /** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor
* @{
*/
#define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 *///8倍频
#define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 *///9倍频
#define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 *///10倍频
#define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 *///11倍频
#define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 *///12倍频
#define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 *///13倍频
#define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 *///14倍频
#define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 *///16倍频
#define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 *///20倍频
|
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
| /** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor
* @{
*/
#define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided *///不分频
#define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 *///2分频
#define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 *//3分频
#define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 *///4分频
#define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 *///5分频
#define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 *///6分频
#define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 *///7分频
#define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 *///8分频
#define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 *///9分频
#define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 *///10分频
#define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 *///11分频
#define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 *///12分频
#define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 *///13分频
#define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 *///14分频
#define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 *///15分频
#define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 *///16分频
|
RCC时钟配置结构体
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
| /**
* @brief RCC System, AHB and APB busses clock configuration structure definition
*/
typedef struct
{
uint32_t ClockType; /*!< The clock to be configured.This parameter can be a value of @ref RCC_System_Clock_Type */
uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.This parameter can be a value of @ref RCC_System_Clock_Source */
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).This parameter can be a value of @ref RCC_AHB_Clock_Source */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
} RCC_ClkInitTypeDef;
|
1
2
3
4
5
6
7
| /** @defgroup RCC_System_Clock_Type System Clock Type
* @{
*/
#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure *///系统时钟
#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure *///总线时钟AHB
#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure *///低速外设时钟APB(APB1)
#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure *///高速外设时钟APB(APB2)
|
1
2
3
4
5
6
| /** @defgroup RCC_System_Clock_Source System Clock Source
* @{
*/
#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock *///内部高速时钟
#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock *///外部高速时钟
#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock *///PLL时钟
|
1
2
3
4
5
6
7
8
9
10
11
12
| /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
* @{
*/
#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided *///不分频
#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 *///2分频
#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 *///4分频
#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 *///8分频
#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 *///16分频
#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 *///64分频
#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 *///128分频
#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 *///256分频
#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 *///512分频
|
- APB1分频器
APB1CLKDivider
- APB2分频器
APB2CLKDivider
1
2
3
4
5
6
7
8
| /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
* @{
*/
#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided *///不分频
#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 *///2分频
#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 *///4分频
#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 *///8分频
#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 *///16分频
|
闪存延时
1
2
3
4
5
6
| /** @defgroup FLASH_Latency FLASH Latency
* @{
*/
#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle *///不延时
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle *///1个延时周期
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles *///2个延时周期
|
gpio.c文件
GPIO结构体分析
1
2
3
4
5
6
7
8
9
10
11
12
13
| /**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured. This parameter can be any value of @ref GPIO_pins_define */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.This parameter can be a value of @ref GPIO_mode_define */
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.This parameter can be a value of @ref GPIO_pull_define */
uint32_t Speed; /*!< Specifies the speed for the selected pins.This parameter can be a value of @ref GPIO_speed_define */
} GPIO_InitTypeDef;
|
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
| /**@defgroup GPIO_pins_define GPIO pins define
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
|
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
| /** @defgroup GPIO_mode_define GPIO mode define
* @brief GPIO Configuration Mode
* Elements values convention: 0xX0yz00YZ
* - X : GPIO mode or EXTI Mode
* - y : External IT or Event trigger detection
* - z : IO configuration on External IT or Event
* - Y : Output type (Push Pull or Open Drain)
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
* @{
*/
#define GPIO_MODE_INPUT 0x00000000u /*!< Input Floating Mode*///输入模式
#define GPIO_MODE_OUTPUT_PP 0x00000001u /*!< Output Push Pull Mode*///推挽输出
#define GPIO_MODE_OUTPUT_OD 0x00000011u /*!< Output Open Drain Mode*///开漏输出
#define GPIO_MODE_AF_PP 0x00000002u /*!< Alternate Function Push Pull Mode*///复用功能推挽输出
#define GPIO_MODE_AF_OD 0x00000012u /*!< Alternate Function Open Drain Mode*///复用功能开漏输出
#define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode*///复用功能输入
#define GPIO_MODE_ANALOG 0x00000003u /*!< Analog Mode*///模拟输入
#define GPIO_MODE_IT_RISING 0x10110000u /*!< External Interrupt Mode with Rising edge trigger detection*///上升沿检测外部中断模式
#define GPIO_MODE_IT_FALLING 0x10210000u /*!< External Interrupt Mode with Falling edge trigger detection*///下降沿检测外部中断模式
#define GPIO_MODE_IT_RISING_FALLING 0x10310000u /*!< External Interrupt Mode with Rising/Falling edge trigger detection*///上升/下降沿检测外部中断模式
#define GPIO_MODE_EVT_RISING 0x10120000u /*!< External Event Mode with Rising edge trigger detection*///上升沿检测外部事件模式
#define GPIO_MODE_EVT_FALLING 0x10220000u /*!< External Event Mode with Falling edge trigger detection*///下降沿检测外部事件模式
#define GPIO_MODE_EVT_RISING_FALLING 0x10320000u /*!< External Event Mode with Rising/Falling edge trigger detection*///上升/下降沿检测外部事件模式
|
1
2
3
4
5
6
7
| /** @defgroup GPIO_pull_define GPIO pull define
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation *///无上拉下拉
#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation*///上拉
#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation*///下拉
|
1
2
3
4
5
6
7
| /** @defgroup GPIO_speed_define GPIO speed define
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed *///低速
#define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed *///中速
#define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed *///高速
|
GPIO常用函数
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
| /**
* @brief Sets or clears the selected data port bit.
*
* @note This function uses GPIOx_BSRR register to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
*
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @param PinState: specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
1
2
3
4
5
6
7
| /**
* @brief Toggles the specified GPIO pin
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
* @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
1
2
3
4
5
6
7
8
| /**
* @brief Reads the specified input port pin.
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
LED输出移植
宏定义输出
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
| /** the macro definition to trigger the led on or off
* 1 - off
*0 - on
*/
#define ON 0
#define OFF 1
#define LED1(a) \
if (a) \
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET); \
else \
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET);
#define LED2(a) \
if (a) \
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_SET); \
else \
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET);
#define LED1_TOGGLE HAL_GPIO_TogglePin(LED1_GPIO_Port,LED1_Pin)
#define LED2_TOGGLE HAL_GPIO_TogglePin(LED2_GPIO_Port,LED2_Pin)
|
主程序调用
1
2
3
4
5
| #define SOFT_DELAY Delay(0x0FFFFF);
void Delay(__IO uint32_t nCount) //简单的延时函数
{
for(; nCount != 0; nCount--);
}
|
1
2
3
4
5
6
7
| LED1(ON); // 亮
SOFT_DELAY;
LED1(OFF); // 灭
LED2(ON); // 亮
SOFT_DELAY;
LED2(OFF); // 灭
|
调试
- 编译并下载到开发板，会看到开发板上两个LED灯在交替闪烁
- 结果和SPL库写的程序输出效果一致